1. Field of the Invention
The present invention relates to a burn-in test method of a semiconductor memory having a bit line twist structure in which bit lines cross each other.
2. Description of the Related Art
Semiconductor memories such as DRAMs have been used as work memories for portable equipments such as mobile phones. In recent years, mobile phones allow users to send character-string data or image data and to access the Internet in addition to allowing the users to make voice communications. The amount of data processed by mobile phones is tending to significantly increase. Accordingly, semiconductor memories having large capacities are in demand.
To increase the memory capacity of a semiconductor memory without increase in cost, memory vendors are moving to decrease the size of the device structures. However, if the distance between adjacent wiring lines is reduced due to the minute size of the device structures, the coupling capacitance between the wiring lines will increase. For example, operation characteristics of DRAMs deteriorate by increased parasitic capacitance between bit lines connected to memory cells.
To reduce data interference between bit lines due to the parasitic capacitance, a bit line twist structure has been proposed in which bit lines cross each other at the central part of a memory cell array. Due to the twist structure, the coupling capacitance between bit lines is reduced and operation characteristics are improved.
On the other hand, a semiconductor memory is generally subjected to a burn-in test during a test process. The burn-in test is an acceleration test for removing an initial failure in a short time by operating the semiconductor memory in a high temperature and high voltage condition. For example, a stress voltage is applied between all adjacent bit lines to remove a product in which a short failure may occur between bit lines or memory cells. Japanese Unexamined Patent Application Publication No. 2004-355720 discloses a burn-in test method of a semiconductor memory having a bit line twist structure. Japanese Unexamined Patent Application Publication No. Hei 10-340598 discloses a burn-in test method in which different voltages are applied to adjacent bit line pairs.
In the above-mentioned burn-in test method, stress is applied between all the bit lines using a plurality of test patterns in which a bit line is set to a high or low voltage level. In the above-mentioned documents, a precharge circuit (equalizer circuit) for setting the bit lines to precharge voltages or a precharge voltage generator is improved to facilitate a plurality of test patterns.
However, in a semiconductor memory having a bit line twist structure, adjacent bit lines are switched within a memory cell array. Therefore, when stress is applied between bit lines, the stress may not be applied to a part of the bit lines. In the above-mentioned burn-in test, in order to reliably remove an inferior product, it is necessary to apply stress between all bit lines for at least a predetermined length of time. If a pattern of voltage application to bit lines is not optimal, the ratio of bit lines to which stress is not applied increases. As a result, burn-in test time increases, which causes the test cost to increase.